A Class of SEC-DED-DAEC Codes Derived From Orthogonal Latin Square Codes – 2015


A Class of SEC-DED-DAEC Codes Derived From Orthogonal Latin Square Codes – 2015


Radiation-induced soft errors are a significant reliability concern for memories. To ensure that memory contents are not corrupted, single error correction double error detection (SEC-DED) codes are commonly used, but, in advanced technology nodes, soft errors frequently have an effect on additional than one memory bit. Since SEC-DED codes cannot correct multiple errors, they are often combined with interleaving. Interleaving, however, impacts memory design and performance and can’t perpetually be used in small memories. This limitation has spurred interest in codes that can correct adjacent bit errors. In particular, many SEC-DED double adjacent error correction (SEC-DED-DAEC) codes have recently been proposed. Implementing DAEC contains a value as it impacts the decoder complexity and delay. Another issue is that most of the new SEC-DED-DAEC codes miscorrect some double nonadjacent bit errors. In this temporary, a brand new class of SEC-DED-DAEC codes is derived from orthogonal latin squares codes. The new codes considerably cut back the decoding complexity and delay. Still, the codes do not miscorrect any double nonadjacent bit errors. The main disadvantage of the new codes is that they require a larger variety of parity check bits. Therefore, they can be helpful when decoding delay or complexity is crucial or when miscorrection of double nonadjacent bit errors isn’t acceptable. The proposed codes are implemented in Hardware Description Language and compared with some of the existing SEC-DED-DAEC codes. The results make sure the reduction in decoder delay.

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