A Novel Approach for High Speed and Low Power 4-Bit Multiplier

A circuit design for a new high speed and Low Power 4-bit Braun Multiplier is presented. The multiplier is implemented by using different power reduction techniques. To design a multiplier it is necessary to design an AND gate and Full Adder circuit using the power reduction techniques is presented. The design uses CMOS digital circuits in order to reduce the power dissipation while maintaining computational throughput.

This paper presents an accurate method of simulating the power dissipation, delay and power delay product, using different techniques in 250nm technology with supply voltage is 2.5v. The power dissipation of nearly 41% and delay 26% has been reduced by using modified proposed technique with good voltage swing levels.

Introduction:
Multiplication is one of the most important operations in digital computer systems because the performance of processors is significantly influenced by the speed of their multipliers and adders. Multiplier plays an important role in the image processor, and sound processor.

High performance multiplier is the important part of the CPU and DSP. Multiplier is one of the most important parameter to determine the processor’s speed. So, designing of multipliers are essential in Very Large Scale Integration (VLSI) systems and Digital Signal Processing (DSP) architectures applications.

Building of low power VLSI system has emerged significant performance goal because of the fast technology in computation. Digital circuit designers have always been encountered in a tradeoff  between speed and power consumption to improve their design’s performance.

The continuing decrease in feature size of CMOS circuits and corresponding increase in chip density and operating frequency have made power consumption a major concern in VLSI design. Different types of multipliers have been proposed earlier like Array Multiplier, Tree Multiplier, and Braun Multiplier.

In this thesis we proposed a new high speed and Low Power 4-bit Braun Multiplier. The multiplier is implemented by using different power reduction techniques. To design a multiplier it is necessary to design an AND gate and Full Adder circuit using the power reduction techniques.
Source: IOSR Journals
Author: P.S.H.S.Lakshmi | S.Rama Krishna | K.Chaitanya

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