Acceleration of EM-Based 3D CT Reconstruction Using FPGA


Acceleration of EM-Based 3D CT Reconstruction Using FPGA


Reducing radiation doses is one of the key issues in computed tomography (CT) based mostly 3D reconstruction. Though iterative strategies such as the expectation maximization (EM) algorithm can be used to address this issue, applying this algorithm to practice is tough thanks to the long execution time. Our goal is to decrease this long execution time to an order of a few minutes, thus that low-dose 3D reconstruction will be performed even in time-critical events. In this paper we tend to introduce a completely unique parallel theme that takes advantage of diverse block RAMs on field-programmable gate arrays (FPGAs). Also, an external memory bandwidth reduction strategy is presented to reuse each the sinogram and therefore the voxel intensity. Moreover, a customized processing engine primarily based on the FPGA is presented to increase overall throughput while reducing the logic consumption. Finally, a hardware and software flow is proposed to quickly construct a style for various CT machines. The whole reconstruction system is implemented on an FPGA-based mostly server-category node. Experiments on actual patient information show that a twenty six.nine speedup can be achieved over a 16-thread multicore CPU implementation.

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