Advanced low power RISC processor design using MIPS instruction set – 2015
Present era of SOC’s comprise analog, digital and mixed signal elements housing on the same chip. In this environment processor plays a very important role. As the technology shrinking to sub-micrometer technology node, there exists an enormous scope of undesirable hazards in processors. These hazards might cause disturbance in area, power and timing which deviate from desired quantities. Our project focuses mainly to resolve some of these problems. In-order to tackle these problems, we are introducing the enhanced version of MIPS. Microprocessor while not Interlocked Pipeline Stages (MIPS) may be a recent architecture into the semi-conductor industry. This project totally concentrates on planning the architecture in Verilog HDL. The planning had been simulated and synthesized in Nc-launch and RTL-compiler licensed by cadence Inc respectively. The physical style of synthesized design had been carried on by Socencounter below slow.lib library of TSMC Cmos 180nm technology node.
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