Aging-Aware Reliable Multiplier Design WithAdaptive Hold Logic – 2015
Digital multipliers are among the most critical arithmetic useful units. The overall performance of those systems depends on the throughput of the multiplier. Meanwhile, the negative bias temperature instability impact happens when a pMOS transistor is underneath negative bias (Vgs = -Vdd), increasing the brink voltage of the pMOS transistor, and reducing multiplier speed. A similar phenomenon, positive bias temperature instability, occurs when an nMOS transistor is beneath positive bias. Both effects degrade transistor speed, and in the long term, the system could fail due to timing violations. Therefore, it’s important to style reliable high-performance multipliers. In this project, we have a tendency to propose an aging-aware multiplier design with a completely unique adaptive hold logic (AHL) circuit. The multiplier is ready to produce higher throughput through the variable latency and can adjust the AHL circuit to mitigate performance degradation that is thanks to the aging impact. Moreover, the proposed architecture will be applied to a columnor row-bypassing multiplier. The experimental results show that our proposed architecture with 16 × 16 and thirty two × 32 column-bypassing multipliers will attain up to 62.eighty eight% and seventy six.twenty eight% performance improvement, respectively, compared with sixteen×sixteen and 32×thirty two mounted-latency column-bypassing multipliers. Furthermore, our proposed architecture with 16 × 16 and thirty two × thirty two row-bypassing multipliers will achieve up to 80.17% and sixty nine.40percent performance improvement as compared with sixteen×sixteen and thirty two × thirty two fixed-latency row-bypassing multipliers.
Did you like this research project?
To get this research project Guidelines, Training and Code… Click Here