An Efficient VLSI Architecture of a Reconfigurable Pulse-Shaping FIR Interpolation Filter for Multistandard DUC – 2015
This brief proposes a 2-step optimization technique for coming up with a reconfigurable VLSI architecture of an interpolation filter for multistandard digital up converter (DUC) to cut back the power and area consumption. The proposed technique initially reduces the number of multiplications per input sample and additions per input sample by 83percent as compared with individual implementation of every normal’s filter while designing a root-raised-cosine finite-impulse response filter for multistandard DUC for three completely different standards. In the following step, a two-bit binary common subexpression (BCS)-based BCS elimination algorithm has been proposed to design an efficient constant multiplier, which is the basic component of any filter. This technique has succeeded in reducing the area and power usage by 41% and 38%, respectively, together with thirty sixpercent improvement in operating frequency over a three-bit BCS-primarily based technique reported earlier, and will be considered a lot of applicable for coming up with the multistandard DUC.
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