An_efficient floating point multiplier design for high speed applications using Karatsuba algorithm and Urdhva-Tiryagbhyam algorithm – 2015
Floating purpose multiplication is a crucial operation in high power computing applications such as image processing, signal processing etc. And conjointly multiplication is the foremost time and power consuming operation. This project proposes an efficient technique for IEEE 754 floating point multiplication which offers a higher implementation in terms of delay and power. A combination of Karatsuba algorithm and Urdhva-Tiryagbhyam algorithm (Vedic Mathematics) is used to implement unsigned binary multiplier for mantissa multiplication. The multiplier is implemented using Verilog HDL, targeted on Spartan-3E and Virtex-4 FPGA.
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