Byte-Reconfigurable LDPC Codec DesignWith Application to High-Performance ECC ofNAND Flash Memory Systems – 2015

PROJECT TITLE:

Byte-Reconfigurable LDPC Codec DesignWith Application to High-Performance ECC ofNAND Flash Memory Systems – 2015

ABSTRACT:

The reliability of NAND Flash memory deteriorates due to multi-level cell technique and advanced manufacturing technology. To cater to additional errors, LDPC codes show superior performance to standard BCH codes as ECC of NAND Flash memory systems. However, LDPC codec for NAND Flash memory systems faces problems of high redesign effort, high on-chip memory cost and high-throughput demand. This project presents a byte-reconfigurable value-effective high-throughput QC-LDPC codec style for NAND Flash memory systems. Reconfigurable codec style is proposed to support various QC-LDPC codes for different Flash memories. To save on-chip memory price, shared-memory design and rescheduling architecture are presented for encoder and decoder, respectively. The shared-memory design can save twenty three% space cost of the encoder and also the rescheduling design reduces fifteen% area cost of decoder. In addition, the proposed sub-iteration based early termination (SIB-ET) scheme reduces twenty nine.six% decoding iteration counts compare with the state-of-the-art early termination theme when raw BER of Flash memory is three×10-three. Finally, the QC-LDPC codec for NAND Flash memory systems is implemented in TSMC 90 nm technology. The post-layout result shows that the core size is solely half-dozen.seventy two mm2 at 22a pair of MHz operating frequency.

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