FPGA implementation of an advanced encoding and decoding architecture of polar codes – 2015

PROJECT TITLE:

FPGA implementation of an advanced encoding and decoding architecture of polar codes – 2015

ABSTRACT:

Polar code, newly formulated by Erdal Arikan, has a wide recognition from the information theory community. Polar code achieves the capability of the category of symmetric binary memory less channels. In this project, we propose efficient hardware architecture on a FPGA platform using Xilinx Virtex VI for implementing the advanced encoding and decoding schemes. The performance of the proposed design out performs the present techniques such as: successive cancellation decoder, list successive cancellation, belief propagation etc; with respect to bit error rate and resource utilization.

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