FPGA realization and performance evaluation of fixed-width modified Baugh-Wooley multiplier – 2015
Mounted-width multipliers are widely employed in digital signal processing (DSP) applications like finite impulse response filter (FIR), quick Fourier rework (FFT) and discrete cosine rework (DCT). Baugh-Wooley multiplier could be a preferred choice for the conclusion of 2’s complement multiplication operation utilized in these applications. This project presents the hardware realization and performance analysis of eight×8 fixed-width modified Baugh-Wooley multiplier using state-of-the-art 7 series field programmable gate arrays (FPGAs) such as Virtex-7, Artix-7 and Zynq-7000, on the market from Xilinx. Different optimization goals are applied to the multiplier style and the performance is evaluated for space, speed and power. Simulation is completed to verify the functionality of the planning.
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