Free Razor: A Novel Voltage Scaling Low-Power Technique for Large SoC Designs

PROJECT TITLE :

Free Razor: A Novel Voltage Scaling Low-Power Technique for Large SoC Designs

ABSTRACT:

This paper proposes a unique voltage scaling low-power design methodology for massive system-on-chip (SoC) styles. It scales the provision voltage to a SoC based mostly on operating conditions and bit error rate in a system. It allows occasional timing errors in the circuit and depends on a forward error correction that already exists within the system to correct the errors. Hence, the proposed technique imposes no hardware overhead yet yields important power savings. A lot of importantly, it does not require any circuit modification primarily based on place and route, therefore it is simple to implement and has no impact for time to market. The new technique was implemented in a very advanced telecom SoC style, and silicon measurements show power savings up to 50percent at no cost.

Did you like this research project?

To get this research project Guidelines, Training and Code… Click Here

COMMENTS :

Leave a Reply

Your email address will not be published. Required fields are marked *

eighteen − = 15