Low-Cost High-Performance VLSI Architecture for Montgomery Modular Multiplication – 2016
This project proposes a straightforward and economical Montgomery multiplication algorithm such that the low-price and high-performance Montgomery modular multiplier can be implemented accordingly. The proposed multiplier receives and outputs the info with binary illustration and uses only one-level carry-save adder (CSA) to avoid the carry propagation at each addition operation. This CSA is also used to perform operand precomputation and format conversion from the carry-save format to the binary representation, leading to an occasional hardware cost and short important path delay at the expense of additional clock cycles for completing one modular multiplication. To overcome the weakness, a configurable CSA (CCSA), that could be one full-adder or two serial 0.5-adders, is proposed to reduce the extra clock cycles for operand precomputation and format conversion by [*fr1]. Yet, a mechanism which will detect and skip the unnecessary carry-save addition operations in the one-level CCSA design whereas maintaining the short important path delay is developed. As a result, the additional clock cycles for operand precomputation and format conversion can be hidden and high throughput can be obtained. Experimental results show that the proposed Montgomery modular multiplier can achieve higher performance and vital area-time product improvement compared with previous designs.
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