Low-Cost High-Performance VLSI Architecture forMontgomery Modular Multiplication. – 2016
This project proposes a straightforward and efficient Montgomery multiplication algorithm such that the low-cost and high-performance Montgomery modular multiplier can be implemented accordingly. The proposed multiplier receives and outputs the information with binary illustration and uses only one-level carry-save adder (CSA) to avoid the carry propagation at each addition operation. This CSA is also used to perform operand precomputation and format conversion from the carry-save format to the binary illustration, leading to a low hardware cost and short essential path delay at the expense of extra clock cycles for finishing one modular multiplication. To overcome the weakness, a configurable CSA (CCSA), that may be one full-adder or 2 serial [*fr1]-adders, is proposed to cut back the additional clock cycles for operand precomputation and format conversion by [*fr1]. In addition, a mechanism that may detect and skip the unnecessary carry-save addition operations in the one-level CCSA architecture while maintaining the short essential path delay is developed. Thence, the additional clock cycles for operand precomputation and format conversion can be hidden and high throughput can be obtained. Experimental results show that the proposed Montgomery modular multiplier can achieve higher performance and important area-time product improvement compared with previous designs.
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