Low Power Multiplier Architectures Using Vedic Mathematics in 45nm Technology for High Speed Computing – 2015
Speed and the performance of any digital signal processor are largely determined by the efficiency of the multiplier units gift among. The use of Vedic mathematics has resulted in vital improvement within the performance of multiplier architectures used for top speed computing. This project proposes 4-bit and eight-bit multiplier architectures primarily based on Urdhva Tiryakbhyam sutra. These low power designs are realized in forty five nm CMOS Method technology using Cadence EDA tool.
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