Modified Wallace Tree Multiplier using Efficient Square Root Carry Select Adder – 2015


Modified Wallace Tree Multiplier using Efficient Square Root Carry Select Adder – 2015


A multiplier is one amongst the key hardware blocks in most digital and high performance systems like FIR filters, micro processors and digital signal processors etc. A system’s performance is generally determined by the performance of the multiplier because the multiplier is usually the slowest element in the whole system and additionally it’s occupying more area consuming. The Carry Select Adder (CSLA) provides a sensible compromise between value and performance in carry propagation adder style. A Square Root Carry Choose Adder using RCA is introduced however it offers some speed penalty. However, standard CSLA continues to be area-consuming because of the twin ripple carry adder structure. Within the proposed work, typically in Wallace multiplier the partial product are reduced while potential and the final carry propagation path carry choose adder is employed. During this project, modification is completed at gate level to scale back area and power consumption. The Modified Sq. Root Carry Choose-Adder (MCSLA) is meant using Common Boolean Logic and then compared with regular CSLA respective architectures, and this MCSLA is implemented in Wallace Tree Multiplier. This work offers the reduced area compared to traditional Wallace tree multiplier. Finally an space economical Wallace tree multiplier is meant using common Boolean logic based square root carry choose adder.

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