On the Analysis of Reversible Booth's Multiplier – 2015


On the Analysis of Reversible Booth’s Multiplier – 2015


Reversible logic attains the attraction of researchers within the last decade mainly because of low-power dissipation. Designers’ endeavors are thus continuing in creating complete reversible circuits consisting of reversible gates. This project presents a design methodology for the belief of Booth’s multiplier in reversible mode. Booth’s multiplier is taken into account collectively of the fastest multipliers in literature and we have shown an economical style methodology in reversible paradigm. The proposed design is capable of performing each signed and unsigned multiplication of two operands without having any feedbacks, whereas existing multipliers in reversible mode take into account loop which is strictly prohibited in reversible logic style. Theoretical underpinnings, established for the proposed design, show that the proposed circuit is terribly economical from reversible circuit design purpose of read.

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