Automatic Parallel Memory Address Generation for Parallel DSP Computing (Computer/Electronics Project)

The concept of Parallel Vector (scratch pad) Memories (PVM) was introduced as one solution for Parallel Computing in DSP, which can provides parallel memory addressing efficiently with minimum latency. The parallel programming more efficient by using the parallel addressing generator for parallel vector memory (PVM) proposed in this project. However, without hiding complexities by cache, the cost of programming is […]

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A Skeleton library for Cell Broadband Engine (Computer Project)

The Cell Broadband Engine processor is a powerful processor capable of over 220 GFLOPS. It is highly specialized and can be controlled in detail by the programmer. The Cell is significantly more complicated to program than a standard homogeneous multi core processor such as the Intel Core2 Duo and Quad. This project explores the possibility to abstract some of the […]

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Modelica PARallel benchmark suite (MPAR) – A test suite for Evaluating the Performance of Parallel Simulations of Modelica Models (Computer Project)

Using the object-oriented, equation-based modeling language Modelica, it is possible to model and simulate computationally intensive models. To reduce the simulation time, a desirable approach is to perform the simulations on parallel multi-core platforms. For this purpose, several works have been carried out so far, the most recent one includes language enhancements with explicit parallel programing language constructs in the […]

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Design and Program Multi-Processor Platform for High-Performance Embedded Processing (Electronics Project)

Modern embedded markets call for high density computing ability, making it is difficult to use just one microprocessor to meet function requirements of high performance embedded systems. Multiple processors, including general-purpose embedded microprocessors, digital signal processors (DSPs), ASICs and FPGA hardware accelerators, are often used in these embedded systems. Not all processors in an embedded device have the same characteristics and […]

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A source-to-source compiler for the PRAM language Fork to the REPLICA many-core architecture (Computer Project)

This study describes the implementation of a source to source compiler that translates Fork language to REPLICA baseline language. The Fork language is a high-level programming language designed for the PRAM (Parallel Random Access Machine) model. The baseline language is a low-level parallel programming language for the REPLICA architecture which implements the PRAM computing model. To support the Fork language […]

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