Reconfigurable architecture of adaptive median filter — An FPGA based approach for impulse noise suppression – 2015
In this project, low complexity reconfigurable hardware architecture for adaptive median filter is proposed and a comparative study of hardware based mostly median and adaptive median filter is presented. An economical development of median & adaptive median filter is presented for removal of impulse noise mainly salt & pepper noise from digital Images. Performance measurement of mean sq. error (MSE) and peak signal-to-noise ratio (PSNR) is finished to match these 2 filters. This project proposes hardware implementation that is highly required for real time execution. Field Programmable Gate Arrays (FPGAs) are widely used for real time processing where the wants of your time, speed, area, power become strict. The algorithms of these 2 filters are mentioned thoroughly that is followed by FPGA based solutions. Simulation is completed using Xilinx ISE 14.five software of XILINX platform where the implementations utilize on Genesys VERTEX V FPGA Board of XC5VLX50T device family.
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