Reverse Converter Design via Parallel-Prefix Adders Novel Components, Methodology, and Implementations – 2015
In this temporary, the implementation of residue number system reverse converters based on well-known regular and modular parallel-prefix adders is analyzed. The VLSI implementation results show a vital delay reduction and area × time2 improvements, all this at the price of upper power consumption, which is the main reason preventing the use of parallel-prefix adders to achieve high-speed reverse converters in today systems. Hence, to unravel the high power consumption drawback, novel specific hybrid parallel-prefix-primarily based adder parts that give better tradeoff between delay and power consumption are herein presented to style reverse converters. A methodology is also described to design reverse converters based mostly on totally different kinds of prefix adders. This technique helps the designer to regulate the performance of the reverse converter based on the target application and existing constraints.
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