Revisiting Central Limit Theorem Accurate Gaussian Random Number Generation in VLSI – 2015

PROJECT TITLE:

Revisiting Central Limit Theorem Accurate Gaussian Random Number Generation in VLSI – 2015

ABSTRACT:

Gaussian random numbers (GRNs) generated by central limit theorem (CLT) suffer from errors because of deviation from ideal Gaussian behavior for any finite variety of additions. In this project, we tend to can show that it is possible to compensate the error in CLT, thereby correcting the resultant chance density operate, significantly in the tail regions. We have a tendency to can offer an in depth mathematical analysis to quantify the error in CLT. This provides a style area with more than four degrees of freedom to make a selection of GRN generators (GRNGs). A framework utilizes this design house to generate customized hardware architectures. We have a tendency to will demonstrate designs of 5 different architectures of GRNGs, which vary in terms of consumed memory, logic slices, and multipliers on field-programmable gate array. Similarly, relying upon application, these architectures exhibit statistical accuracy from low (4s) to extremely high (12s). A comparison with previously published styles clearly indicate blessings of this technique in terms of both consumed hardware resources and accuracy. We have a tendency to can additionally offer synthesis results of same designs in application-specific integrated circuit using 65-nm normal cell library. Finally, we have a tendency to will highlight some shortcomings associated with such architectures followed by their remedies.

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