Run-time reconfigurable multi-precision floating point multiplier design for high speed, low-power applications – 2015
Floating purpose multiplication is one among the crucial operations in several application domains like image processing, signal processing etc. But each application needs completely different working options. Some want high precision, some would like low power consumption, low latency etc. But IEEE-754 format is not very flexible for these specifications and conjointly style is complex. Optimal run-time reconfigurable hardware implementations may would like the employment of custom floating-point formats that don’t essentially follow IEEE specified sizes. In this project, we present a run-time-reconfigurable floating purpose multiplier implemented on FPGA with custom floating purpose format for various applications. This floating purpose multiplier will have 6 modes of operations depending on the accuracy or application demand. With the employment of optimal design with custom IPs (Intellectual Properties), a better implementation is done by truncating the inputs before multiplication. And a mixture of Karatsuba algorithm and Urdhva-Tiryagbhyam algorithm (Vedic Mathematics) is employed to implement unsigned binary multiplier. This any increases the potency of the multiplier.
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