TM-RF Aging-Aware Power-Efficient Register File Design for Modern Microprocessors – 2015

PROJECT TITLE:

TM-RF Aging-Aware Power-Efficient Register File Design for Modern Microprocessors – 2015

ABSTRACT:

Modern microprocessors use register files (RFs) for performance enhancement and achieving instruction level parallelism simultaneously. However, RF incurs massive power consumption attributable to the highly frequent access. Meanwhile, as technology scales, bias temperature instability has become a major reliability concern for RF designers. This project presents an aging-aware trimodal register file (TM-RF) style to enhance the facility efficiency. As instructions suffer the pipeline, TM-RF places the bit-cells in several modes based on the register activity, thereby achieving vital power reduction. To meet style constraints of different applications, we have a tendency to gift four schemes to implement the proposed style, providing style flexibility. Additionally, with device choice and worst case sizing methodology, we have a tendency to mitigate aging-impact-induced RF reliability degradation. Simulation results on SPEC 2000 benchmarks demonstrate that TM-RF achieves up to 81.fourp.c power savings and seventeen% reliability improvement on average, with minimal impact on performance.

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